1. Technical Field
The present disclosure relates to a semiconductor memory device and, more particularly, to a method of compensating for signal interference of the semiconductor memory device.
2. Discussion of the Related Art
In order to realize high-capacity high-speed semiconductor memory devices, pairs of local data input/output lines are disposed as data input/output lines, and column selection signal lines and pairs of global data input/output lines are disposed in a direction orthogonal to the pairs of local data input/output lines.
However, as the integration density of semiconductor memory devices increases, signal intensity decreases and the number of signal lines increases. Thus, it is necessary to dispose a greater number of signal lines and circuits in limited areas of the semiconductor devices so as to minimize the load of signal lines.
In a conventional semiconductor memory device, when a signal is applied to a column selection signal line to read data from a memory cell, data is transmitted via a pair of global data input/output lines to a global data input/output multiplexer in response to the applied signal.
The column selection signal line is a full-swing signal line that transitions from a power supply voltage to a ground voltage, and the pair of global data input/output lines are a pair of small-swing signal lines that transition from a precharge level to a complementary level. When the column selection signal line is in a full swing, the pair of global data input/output lines are affected by interference due to coupling capacitances between the column selection signal line and the pair of global data input/output lines.
That is, when a signal is applied to a column selection signal line disposed adjacent to the pair of global data input/output lines, interference occurs at the pair of small-swing global data input/output lines so that a signal applied to the pair of small-swing global data input/output lines is delayed, as compared to when no interference occurs, before it is transmitted to the global data input/output multiplexer.
As a result, a data read speed of the entire semiconductor memory device is degraded. Furthermore, with the development of high-capacity semiconductor memory devices, the length of the pair of global data input/output lines continues to increase, further degrading the data read speed and affecting the performance of the entire semiconductor memory device.
Various methods have been proposed to address the above issues. For example, a signal line for transmitting global input/output data signals with very low intensity may be shielded using power lines to avoid coupling with other signal lines. Alternatively, interference caused by a column selection signal line may be reduced by half using a pair of twisted global data input/output lines GI01-GI0B, as shown in FIG. 1.
FIG. 1 is a block diagram of a conventional semiconductor memory device using a pair of twisted global data input/output lines.
Referring to FIG. 1, the semiconductor memory device includes four memory cell array blocks BL1 to BL4, a plurality of local data input/output lines (LIO1, LIO1B) to (LIO4, LIO4B), a word line WL, a plurality of column selection signal lines CSL1 to CSLn, a plurality of global data input/output lines (GIO1, GIO1B), (GIO2, GIO2B), . . . , and a column address decoder 10.
An upper left memory array region of the semiconductor memory device including the memory cell array blocks BL1 to BL4, the local data input/output lines (LIO1, LIO1B) to (LIO4, LIO4B), the column selection signal lines CSL1 to CSLn, and the global data input/output lines (GIO1, GIO1B), (GIO2, GIO2B), . . . will be described. A memory cell MC, a bit line sense amplifier BLSA, and a column selection circuit 20 are connected between the word line WL and a pair of bit lines BLP1. A local input/output sense amplifier Local IOSA is disposed at an intersection point between the pair of local data input/output lines LIO1 and LIO1B and the pair of global data input/output lines GIO1 and GIO1B. Also, an input/output sense amplifier IOSA and a global input/output multiplexer GIOMUX are connected between the pair of global data input/output lines GIO1 and GIO1B.
As can be seen from FIG. 1, the word line WL and the plurality of column selection signal lines CSL1 to CSLn are adjacently arranged in the same direction as, or in an orthogonal direction to, the plurality of local data input/output lines (LIO1, LIO1B) to (LIO4, LIO4B), and the plurality of global data input/output lines (GIO1, GIO1B), (GIO2, GIO2B), . . . are twisted pairs.
Functions of respective blocks of the conventional semiconductor memory device will now be described with reference to FIG. 1.
A memory cell MC receives a signal of the word line WL, which is enabled in response to a row address, and outputs written/stored data to a pair of bit lines BL and BLB.
The bit line sense amplifier BLSA receives charges stored in a capacitor of the memory cell MC via the pair of bit lines BL and BLB and amplifies a voltage corresponding to the charges.
The column address decoder 10 receives a column address CA, decodes the column address CA, and enables one of a plurality of column selection signals CSL1, CSL2, . . . , and CSLn of the four memory cell array blocks BL1 to BL4.
The column selection circuit 20 is composed of two NMOS transistors N1 and N2 each having one terminal to which a pair of output signals LIO and LIOB of the bit line sense amplifier BLSA are applied, respectively, and gate terminals to which the column selection signal CSL1 is applied. The column selection circuit 20 externally receives a column address along with a read command, turns on the NMOS transistors N1 and N2 in response to the enabled column selection signal CSL1, and transmits data signals of the pair of sensed bit lines BL and BLB to the pair of local input/output lines LIO and LIOB.
The local input/output sense amplifier Local IOSA receives data of the transmitted bit line signals BL and BLB, amplifies a voltage difference between the bit line signals BL and BLB, and outputs an amplified signal, thereby preventing an operating speed from being degraded due to a load mismatch between the pair of local input/output lines LIO and LIOB having a small load, and the pair of global input/output lines GIO and GIOB having a large load.
The global data input/output multiplexer GIOMUX receives the amplified signal from the local input/output sense amplifier Local IOSA through the global input/output lines GIO and GIOB, converts N-bit parallel data of the pair of global input/output lines GIO and GIOB into M serial data, and outputs the converted data.
The input/output sense amplifier IOSA receives the converted serial data of the global input/output lines GIO and GIOB, amplifies a voltage difference between the received data, and outputs an amplified signal.
FIG. 2 is a circuit diagram for modeling a coupling capacitance between a column selection signal line (CSL1) and a pair of global data input/output lines (GI01, GI01B) in the conventional semiconductor memory device shown in FIG. 1.
The column selection signal line CSL1 and the pair of global data input/output lines GIO1 and GIOB1 are divided into three portions. A coupling capacitance between the column selection signal line CSL1 and the global data input/output line GIO1 includes capacitances CA1, CB3, CC1, and CD3. A coupling capacitance between the pair of global data input/output lines GIO1 and GIO1B includes capacitances CA2, CB2, CC2, and CD2. Also, a coupling capacitance between the column selection signal line CSL1 and the global data input/output line bar GIO1B includes capacitances CA3, CB1, CC3, and CD1.
During the enabling and disabling of the column selection signal line CSL1, the sum (CA1+CC1) of the coupling capacitances between the column selection signal line CSL1 and the global data input/output line GIO1 affects the global data input/output line GIO1 causing a voltage variation in the global data input/output line GIO1. Also, the sum (CB1+CD1) of the coupling capacitances between the column selection signal line CSL1 and the global data input/output line bar GIO1B affects the global data input/output line bar GIO1B causing a voltage variation in the global data input/output line bar GIO1B.
Accordingly, the voltage variations in the pair of twisted global data input/output lines GIO1 and GIO1B caused by a voltage variation in the column selection signal line CSL1 are reduced compared to when a pair of global data input/output lines GIO1 and GIO1 are not twisted.
For example, assuming that each of the coupling capacitances CA1, CB1, CC1, and CD1 is equal to a capacitance C, in the conventional semiconductor memory device including the pair of untwisted global data input/output lines GIO1 and GIO1B, a voltage of the global data input/output line GIO1 is largely affected by a voltage variation in the column selection signal line CSL1 due to a coupling capacitance 4C between the column selection signal line CSL1 and the global data input/output line GIO1. In contrast, in the semiconductor memory device shown in FIG. 1, the coupling capacitance between the column selection signal line CSL1 and the global data input/output line GIO1, and the coupling capacitance between the column selection signal line CSL2 and the global data input/output line GIO1B, is reduced to a capacitance 2C, thereby reducing a voltage variation in the pair of global data input/output lines GIO1 and GIO1B caused by a voltage variation in the column selection signal line CSL1. FIG. 3 is a timing diagram illustrating the operation of a memory cell array block BL1 of the conventional semiconductor memory device shown in FIG. 1.
The operation of the memory cell array block BL1 is affected by the input and output of a row address strobe signal RASB, a column address strobe signal CASB, an address signal ADD, a write enable signal WEB, a word line enable signal WL, a precharge signal PRE, a first column selection signal CSL1, a second column selection signal CSL2, a pair of bit line signals BLP1, a pair of local data input/output line signals LIO1 and LIO1B, and a pair of global data input/output line signals GIO1 and GIO1B.
In FIG. 3, assuming that a high-level inverted write enable signal WEB is applied to read low-level data from the pair of bit lines BLP1, when a low-level row address strobe signal RASB is applied, the address signal ADD loads a row address X, and when a low-level column address strobe signal CASB is applied, the address signal ADD loads a column address Y1.
The row address X is decoded to generate a high-level word line enable signal WL, and the column address Y1 is decoded to generate a high-level column selection signal CSL1.
Also, when a high-level precharge signal PRE is generated before the high-level word line enable signal WL is generated, the pair of bit lines BLP1, the pair of local data input/output lines LIO1 and LIO1B, and the pair of global data input/output lines GIO1 and GIO1B are precharged in response to the high-level precharge signal PRE.
When the high-level word line enable signal WL is generated, a voltage difference between data signals transmitted to the pair of bit lines BLP1 develops, and the bit line sense amplifier BLSA amplifies the voltage difference between the data signals transmitted to the pair of bit lines BLP1 to a complementary level.
When the high-level column selection signal CSL1 is generated, the data signals of the pair of bit lines BLP1 are respectively transmitted to the pair of local data input/output lines LIO1 and LIO1B, transmitted to the pairs of global data input/output lines GIO1 and GIO1B, and amplified by the input/output sense amplifier IOSA.
Meanwhile, after a predetermined time elapses, when the column address strobe signal CASB returns to a low level and the address signal ADD loads a column address Y2, the column address decoder 10 decodes the column address Y2 and generates a high-level second column selection signal CSL2.
Thus, when the first column selection signal CSL1 is enabled to a high level, a voltage difference between data signals transmitted to the pair of bit lines BLP1 develops so that the bit line sense amplifier BLSA amplifies the voltage difference between the data signals transmitted to the pair of bit lines BLP1 to a complementary level, and the data signals of the pair of bit lines BLP1 are respectively transmitted to the pair of local data input/output lines LIO1 and LIO1B and the pair of global data input/output lines GIO1 and GIO1B, and amplified by the input/output sense amplifier IOSA.
However, since the global data input/output line bar signal GIO1B is being interfered by the second column selection signal CSL2, the phases of the pair of global data input/output line signals GIO1 and GIO1B are opposite to the phases of the pair of global data input/output line signals GIO1 and GIO1B generated when the global data input/output line signal GIO1 is being interfered by the first column selection signal CSL1.
When the voltage difference between the data signals transmitted to the pair of global data input/output lines GIO1 and GIO1B is produced, the input/output sense amplifier IOSA senses and amplifies the voltage difference between the data signals transmitted to the pair of global data input/output lines GIO1 and GIO1B. Therefore, because the moment when the voltage difference between the data signals transmitted to the pair of global data input/output lines GIO1 and GIO1B is earlier, a read access time becomes shorter.
However, in the conventional semiconductor memory device, when the twisted pair of global data input/output lines GIO1 and GIO1B is disposed adjacent to the column selection signal line CSL1, a coupling capacitance exists between the twisted pair of global data input/output lines GIO1 and GIO1B as shown in FIG. 2. Thus, the coupling capacitance between the twisted pair of global data input/output lines GIO1 and GIO1B affects the data signals transmitted thereto.
In other words, during the enabling and disabling of the column selection signal line CSL1, a voltage of the twisted pair of global data input/output lines GIO1 and GIO1B is affected by a small capacitance and instantaneously rises or drops to a voltage that is lower by ΔV1 than in the conventional semiconductor memory device including the pair of untwisted global data input/output lines GIO1 and GIO1B.
Thus, because the moment when the voltage difference between the data signals transmitted to the pair of global data input/output lines GIO1 and GIO1B is produced is earlier by ΔT1 than in the conventional semiconductor memory device, including the pair of untwisted global data input/output lines GIO1 and GIO1B, a read data access time is improved.
However, since the conventional semiconductor memory device shown in FIG. 1 includes the twisted pair of global data input/output lines GIO1 and GIO1B, layers of the pair of global data input/output lines GIO1 and GIO1B need to be changed using contacts (e.g., vias). As a result, transmitted signals are delayed due to proper resistance elements, and the pair of global data input/output lines GIO1 and GIO1B is highly likely to be positionally deviated during a semiconductor fabrication process.
Furthermore, since data written to or read from the actual memory cell MC is transmitted through the pair of global data input/output lines GIO1 and GIO1B, when the pair of global data input/output lines GIO1 and GIO1B is positionally deviated, not only data read performance but also data write performance may be degraded, and data encoding must be reversed at portions where the pair of global data input/output lines GIO1 and GIO1B are twisted, thereby complicating circuit design.